The present patent application is a continuation patent application of and claims priority to U.S. application Ser. No. 12/052,271 (now U.S. Pat. No. 7,768,817), filed Mar. 20, 2008, entitled “VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE,” invented by Shigekazu Yamada, the disclosure of which is incorporated by reference herein.
As memory technology heads towards products that use less power, and are lighter and more robust, flash memory products stand out as a good alternative over other storage solutions. Its ability to efficiently program, read, and erase blocks of data at a time is attractive.
In recent years, the programming performance of flash memory products has been enhanced, thus satisfying customers who prefer fast-programming, for example, greater than 10 Mb/sec. Other customers prefer low power consumption, for example, for simultaneous multi-chip usage over the need for such a high speed.
In general, bit line-charging during programming accounts for a large part of power consumption. In part, this is due to the lengthiness of bit lines. Most of the NAND flash memory products have the capability to suppress the charging current. However, it is difficult to control the charging current accurately due to RC delay changes due to variations in temperature and transistor models. As a result, data registers may be at a higher risk of malfunctions due to a larger charging current.